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esi esi 1 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. es29lv320e 32mbit(4m x 8/2m x 16) cmos 3.0 volt-only, boot sector flash memory general features ? single power supply operation - 2.7v ~ 3.6v for read , program and erase operations ?sector structure - 8kbyte x 8 boot sectors - 64kbyte x 63 sectors - 256byte security sector ? top or bottom boot block - es29lv320et for top boot block device - es29lv320eb for bottom boot block device ? a 256 bytes of extra sector for security code - factory locked - customer lockable ? package options - 48-pin tsop - 48-ball fbga - pb-free packages - all pb-free products are rohs-compliant ? low vcc write inhibit ? manufactured on 0.18um process technology ? compatible with jedec standards - pinout and software compatible with single-power supply flash standard device performance ? read access time - 70ns/90ns for normal vcc range ( 2.7v ~ 3.6v ) ? program and erase time - program time : 6us/byte, 8us/word ( typical ) - accelerated program ti me : 4us/word ( typical ) - sector erase time : 0.7sec/sector ( typical ) ? power consumption (typical values) - 15ua in standby or automatic sleep mode - 10ma active read current at 5mhz - 15ma active write current during program or erase ? minimum 100,000 program/erase cycles per sector ? 20 year data retention at 125 o c software features ? erase suspend / erase resume ? data# poll and toggle for program/erase status ? cfi ( common flash interface) supported ? unlock bypass program ? autoselect mode ? auto-sleep mode after t acc + 30ns hardware features ? hardware reset input pin (reset#) - provides a hardware reset to device - any internal device operation is terminated and the device returns to read mode by the reset ? ready/busy# output pin (ry/by#) - provides a program or erase operational status about whether it is finished for read or still being progressed ? wp#/acc input pin - two outermost boot sectors are protected when wp# is set to low, regardless of sector protection - program speed is accelerated by raising wp#/acc to a high voltage (11.5v~12.5v) ? sector protection / unpr otection (reset# , a9 ) - hardware method of locking a sector to prevent any program or erase operation within that sector - two methods are provided : - in-system method by reset# pin - a9 high-voltage method for prom programmers ? temporary sector unprotecti on (reset# ) - allows temporary un protection of previously protected sectors to change data in-system
esi esi 2 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. the es29lv320 is a 32 megabit, 3.0 volt-only flash memory device, organized as 4m x 8 bits (byte mode) or 2m x 16 bits (word mode) which is config- urable by byte#. eight bo ot sectors and sixty three main sectors with uniform size are provided : 8kbytes x 8 and 64kbytes x 63. the device is man- ufactured with esi?s proprietary, high performance and highly reliable 0.18um cmos flash technology. the device can be programmed or erased in-sys- tem with standard 3.0 volt vcc supply ( 2.7v~3.6v) and can also be programmed in standard eprom programmers. the device offers minimum endur- ance of 100,0 00 program/erase cycles and more than 10 years of data retention. the es29lv320 offers access time as fast as 70ns or 90ns, allowing operation of high-speed micropro- cessors without wait states. three separate control pins are provided to eliminate bus contention : chip enable (ce#), write enable (we#) and output enable (oe#). all program and erase operation are automatically and internally performed and controlled by embed- ded program/erase algorithms built in the device. the device automatically generates and times the necessary high-voltage pulses to be applied to the cells, performs the verifi cation, and counts the num- ber of sequences. some status bits (dq7, dq6 and dq5) read by data# po lling or toggling between consecutive read cycles provide to the users the internal status of program/erase operation: whether it is successfully done or still being progressed. extra security sector of 256 bytes in the device, an extra secu rity sector of 256 bytes is provided to customers. this extra sector can be used for various purposes such as storing esn (electronic serial number) or customer?s security codes. once after the extra se ctor is written, it can be permanently locked by the device manufacturer ( factory-locked ) or a customer( customer-lockble ). at the same time, a lock indicator bit ( dq7 ) is per- manently set to a 1 if the part is factory- locked, or set to 0 if it is customer-lockable. therefore, this lock indicator bit (dq7) can be properly used to avoid that any customer-lockable part is used to replace a factory-locked part. the ex tra security sector is an extra memory space for customers when it is used as a customer-lockable version. so, it can be read and written like any other sectors. but it should be noted that the number of e/w(erase and write) cycles is limited to 300 ti mes (maximum) only in the security sector. special services such as esn and factory-lock are available to customers (esi?s special-code service ) the es29lv320 is completely compatible with the jedec standard command set of single power sup- ply flash. commands are written to the internal command register using standard write timings of microprocessor and data can be read out from the cell array in the device with the same way as used in other eprom or flash devices. general product description
esi esi 3 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. product selector guide family part number es29lv320e voltage range 2.7v ~ 3.6 v speed option 70 90 max access time (ns) 70 90 ce# access (ns) 70 90 oe# access (ns) 30 40 command register analog bias generator address latch byte# ce# oe# a<0:20 > reset# vcc vss chip enable output enable logic vcc detector timer/ counter y-decoder x-decoder y-decoder cell array data latch/ sense amps input/output buffers sector switches dq0-dq15(a-1) ry/by# write state machine we # function block diagram
esi esi 4 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. pin description pin description a0-a20 21 addresses dq0-dq14 15 data inputs/outputs dq15/a-1 dq15 (data input/output, word mode) a-1 (lsb address input, byte mode) ce# chip enable oe# output enable we# write enable wp#/acc hardware write protect/acceleration pin reset# hardware reset pin, active low byte# selects 8-bit or 16-bit mode ry/by# ready/busy output vcc 3.0 volt-only single power supply (see product selector guide for s peed options and voltage supply tolerances) vss device ground nc pin not connected internally logic symbol dq0 ~ dq15 (a-1) ry/by# byte# reset# oe# ce# a0 ~ a20 wp#/acc we# 21 16 or 8
esi esi 5 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. connection diagram a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# nc wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 a16 byte# vss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 vcc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48-pin standard tsop es29lv320e 48-ball fbga 6 x 8 mm) (top view, balls facing down) a13 a12 a14 a15 a16 dq15/ vss a9 we# oe# ce# a0 a1 a2 a4 wp#/ a11 dq7 dq14 dq13 dq6 nc a19 a18 dq5 a20 a5 dq2 dq0 dq8 dq9 dq1 dq10 dq11 dq3 dq12 vcc dq4 a3 a10 c d e f g h j k 7 6 5 4 3 2 byte# a-1 a8 reset# ry/ a7 a17 a6 vss acc by#
esi esi 6 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. several device operational modes are provided in the es29lv320 device. commands are used to ini- tiate the device operations . they are latched and stored into internal registers with the address and data information needed to execute the device operation. the available device operational modes are listed in table 1 with the required inputs, controls, and the resulting outputs. each operational mode is described in further detail in the following subsec- tions. read the internal state of the device is set for the read mode and the device is ready for reading array data upon device power-up, or after a hardware reset. to read the stored data from the cell array of the device, ce# and oe# pins should be driven to v il while we# pin remains at v ih . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. word or byte mode of output data is determined by the byte# pin. no additional command is needed in this mode to obtain array data. standard micro- processor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device stays at the read mode until another operation is activated by writing commands into the internal command register. refer to the ac read cycle timing diagrams for further details ( fig. 18 ). word/byte mode configuration ( byte# ) the device data output can be configured by byte# into one of two modes : word and byte modes . if the byte# pin is set at logic ?1?, the device is configured in word mode, dq0 - dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is configured in byte mode, and only data i/o pins dq0 - dq7 are active and controlled by ce# and oe#. the data i/o pins dq8 - dq14 are tri- stated, and the dq15 pin is used as an input for the lsb (a-1) address. standby mode when the device is not se lected or activated in a system, it needs to stay at the standby mode, in which current consumption is greatly reduced with outputs in the high impedance state. device bus operations
esi esi 7 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. the device enters the cmos standby mode when ce# and reset# pins are both held at vcc + 0.3v. (note that this is a more restricted voltage range than v ih. ) if ce# and reset# are held at v ih , but not within vcc + 0.3v, the device will be still in the standby mode, but the standby current will be greater than the cmos standby current (0.2ua typi- cally). when the device is in the standby mode, only standard access time (t ce ) is required for read access, before it is ready for read data. and even if the device is deselected by ce# pin during erase or programming operation, the device draws active cur- rent until the operation is completely done. while the device stays in the standby mode, the output is placed in the high impedance state, independent of the oe# input. the device can enter the deep power-down mode where current consumption is greatly reduced down to less than 15ua typica lly by the following three ways: - cmos standby ( ce#, reset# = vcc + 0.3v ) - during the device reset ( reset# = vss + 0.3v ) - in autosleep mode ( after t acc + 30ns ) refer to the cmos dc characteristics table11 for further current specification. autosleep mode the device automatically enters a deep power-down mode called the autosleep mode when addresses remain stable for t acc +30ns. in this mode, current consumption is greatly reduced ( less than 15ua typ- ical ), regardless of ce#, we# and oe# control sig- nals. writing commands to write a command or command sequences to ini- tiate some operations such as program or erase, the system must drive we# and ce# to v il , and oe# to v ih . for program operations, the byte# pin deter- mines whether the device accepts program data in bytes or words. refer to ?byte# timings for write operations? in the fig. 21 for more information. unlock bypass mode to reduce more the programming time, an unlock- bypass mode is provided. once the device enters this mode, only two write cycles are required to ini- tiate the programming operation instead of four cycles in the normal program command sequences which are composed of two unlock cycles, program set-up cycle and the last cycle with the program data and addresses. in this mode, two unlock cycles are saved ( or bypassed ). sector addresses the entire memory space of cell array is divided into a many of small sectors: 8kbytes x 8 boot sec- tors and 64kbytes x 63 main sectors. in erase operation, a single sector, multiple sectors, or the entire device (chip erase) can be selected for erase. the address space that each sector occu- pies is shown in detail in the table 3-4. accelerated program mode the device offers accelerated program operations through the acc function. th is is one of two func- tions provided by the wp#/acc pin. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh (11.5v~12.5v) on this pin, the device automatically enters the previously mentioned unlock bypass mode , temporarily unprotects any protected sec- tors, and uses the higher voltage on the pin to reduce the time required for program operations. only two-cycle program command sequences are required because the unlock bypass mode is auto- matically activated in th is acceleration mode. the device returns to the normal operation when v hh is removed from the wp#/acc pin. it should be noted that the wp#/acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. in addition, the wp#/ acc pin must not be left floating or unconnected; inconsistent or undesired behavior of the device may result. autoselect mode flash memories are intended for use in applica- tions where the local cpu alters memory contents. in such applications, manufacturer and device identification (id) code s must be accessible while the device resides in the target system ( the so called ?in-system program? ). on the other hand, signature codes have been typically accessed by raising a9 pin to a high voltage in prom program- mers. however, multiplexing high voltage onto address lines is not the generally desired system design practice. therefore, in the es29lv320 device an autoselect command is provided to allow the system to access the signature codes without any high voltage. the conventional a9 high-voltage method used in the prom program- ers for signature codes ar e still supported in this device.
esi esi 8 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. if the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read some useful codes such as manufacturer and device id from the internal reg- isters on dq7 - dq0. standard read cycle timings apply in this mode. in the autoselect mode, the fol- lowing four informations can be accessed through either autoselect command method or a9 high-volt- age autoselect method. refer to the table 2. - manufacturer id - device id - security sector lock-indicator - sector protection verify hardware device reset ( reset# ) the reset# pin provides a hardware method of resetting the device to read array data. when the reset# pin is driven low for at least a period of t rp , the device immediately te rminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once after the device is ready to accept another command sequence, to ensure data integrity. cmos standby during device reset current is reduced for the duration of the reset# pulse. when reset# is held at vss + 0.3v, the device draws the greatly reduced cmos standby current ( i cc4 ). if reset# is held at v il but not within vss + 0.3v, the standby curr ent will be greater. ry/by# and terminating operations if reset# is asserted dur ing a program or erase operation, the ry/by# pin remains a ?0? (busy) until the internal reset operation is completed, which requires a time of t ready (during embedded algo- rithms). the system can thus monitor ry/by# to determine whether the reset operation is completed. if reset# is asserted wh en a program or erase operation is not executing (ry/by# pin is ?1?), the reset operation is completed within a time of t ready (not during embedded algo rithms). the system can read data after the reset# pin returns to v ih , which requires a time of t rh. reset# tied to the system reset the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory.refer to the ac characteristics ta bles for reset# parame- ters and to fig. 19 fo r the timing diagram. sector group protection the es29lv320 features hardware sector group protection. a sector group consists of two or more adjacent sectors that are protected or unprotected at the same time. in the de vice, sector protection is performed on the group of sectors previously defined in the table 3-4. once after a group of sec- tors are protected, any pr ogram or erase operation is not allowed in the protected sector group. the previously protected sect ors must be unprotected by one of the unprotect methods provided here before changing data in those sectors. sector pro- tection can be implemented via two methods. - in-system protection - a9 high-voltage protection to check whether the sect or group protection was successfully executed or not, another operation called ? protect verification ? needs to be performed after the protection operation on a group of sectors. all protection and protect verifications provided in the device are summarized in detail at the table 1. in-system protection ?in-system protection?, the primary method, requires v id (11.5v~12.5v) on the reset# with a6=0, a1=1, and a0=0. this method can be imple- mented either in-system or via programming equip- ment. this method uses standard microprocessor bus cycle timing. refer to fig. 29 for timing diagram and fig. 3 for the protection algorithm. a9 high-voltage protection ?high-voltage protection?, the alternate method intended only for programming equipment, must force v id (11.5v~12.5v) on address pin a9 and control pin oe# with a6=0, a1=1 and a0=0. refer to fig. 31 for timing diagram and fig. 5 for the pro- tection algorithm. sector unprotection the previously protected sectors must be unpro- tected before modifying any data in the sectors. the sector unprotection al gorithm unprotects all sectors in parallel. all unprotected sectors must first
esi esi 9 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. be protected prior to the first sector unprotection write cycle to avoid any over-erase due to the intrin- sic erase characteristics of the protection cell. after the unprotection operation, all previously protected sectors will need to be individually re-protected. standard microprocessor bus cycle timings are used in the unprotection and un protect verification opera- tions. three unprotect methods are provided in the es29lv320 device. all unprotection and unprotect verification cycles are summarized in detail at the table 1. - in-system unprotection - a9 high-voltage unprotection - temporary sector unprotection in-system unprotection ?in-system unprotection ?, the primary method, requires v id (11.5v~12.5v) on the reset# with a6=1, a1=1, and a0=0. this method can be imple- mented either in-system or via programming equip- ment. this method uses standard microprocessor bus cycle timing. refer to fi g. 29 for timing diagram and fig. 4 for the unprotection algorithm. a9 high-voltage unprotection ?high-voltage unprotection?, the alternate method intended only for programming equipment, must force v id (11.5v~12.5v) on address pin a9 and con- trol pin oe# with a6=1, a1=1 and a0=0. refer to fig. 32 for timing diagram and fig. 6 for the unpro- tection algorithm. temporary sector unprotect this feature allows tempor ary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the reset# pin to v id (11.5v~12.5v). during this mode, formerly protected sectors can be pro- grammed or erased by selecting the sector addresses. once v id is removed fr om the reset# pin, all the previously protected sectors are pro- tected again. fig. 1 shows the algorithm, and fig. 27 shows the timing diagrams for this feature. write protect ( wp# ) the write protect function provides a hardware method of protecting certain boot sectors without using v id . this function is one of two provided by the wp#/acc pin. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the two ?outermost? 8kbytes boot sectors indepen- dently of whether those sectors were protected or unprotected using the method described in ?sector group protection and unpr otection?. the two outer- most of 8 kbyte boot sectors are the two sectors containing the lowest addresses in a bottom-boot- configured device, or the two sectors containing the highest addresses in a top-boot-configured device. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the two outermost 8 kbyte boot sectors were la st set to be protected or unprotected. that is, sector protection or unprotec- tion for these two sectors depends on whether they were last protected or unprotected using the method described in ?sector group protection and unprotection?. note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. notes: 1. all protected sectors are unprotected (if wp#/acc = v il , outermost boot sectors will remain protected). 2. all previously protected sectors are protected once again. figure 1. temporary sector unprotect operation start reset# = v id (note 1) perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2)
esi esi 10 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. security sector the security sector of the es29lv320 device pro- vides an extra flash memory space that enables permanent part identification through an electronic serial number (esn). the security sector uses a security lock-indicator bit (dq7) to indicate whether or not the security sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which pre- vents cloning of a factory locked part. this ensures the security of the esn on ce the product is shipped to the field . note that the es29lv320 has a security sector size of 256 bytes . security lock-indicator bit (dq7) in the device, the security sector can be provided in either factory lo cked version or cu stomer lockable version. the factory-locked version is always pro- tected when shipped from the factory, and has the security lock-indicator bit permanently set to a ?1?. the customer-lockable version is shipped with the security sector unprot ected, allowing customers to utilize the sector in any manner they choose. the customer-lockable version has the security lock- indicator bit permanently set to a ?0?. thus, the security lock-indicator bi t prevents customer-lock- able devices from being used to replace devices that are factory locked. access to the security sector the security sector can be accessed through a command sequence: enter security and exit security sector commands. after the system has written the enter secu rity sector command sequence, it may read the security sector by using the addresses normally occupied by the boot sec- tors. this mode of operati on continues until the sys- tem issues the exit security sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device returns to read mode in which the nor- mal boot sectors can be accessed, instead of the security sector. factory-locked device in a factory-locked device, the security sector is protected when the device is shipped from the fac- tory. the security sector cannot be modified in any way. the device is available preprogrammed with one of the following: - a random, secure esn (16 bytes ) only - customer code through the esi?s special-code service - both a random, secure esn and customer code through the esi?s special-code service. esn ( electronic serial number ) in devices that have an esn, a bottom boot device will have the 16-byte (8-w ord) esn in sector 0 at addresses 000000h-00000fh in byte mode (or 000000h-000007h in word mode). in the top boot device the esn will be in sector 70 at addresses 3fff00h-3fff0fh in byte mode (or 1fff80h- 1fff87h in word mode). note that in upcoming top boot versions of this devi ce, the esn will be located in sector 70 at addresses 3fff00h-3fff0fh in byte mode (or 1fff80h-1fff87h in word mode). esi?s special-code service customers may opt to have their code programmed by esi through the esi?s special-code service. esi programs the customer?s code, with or without the random esn. the devices are then shipped from esi?s factory with the security sector permanently locked. contact an esi representative for details on using esi?s special-code service. customer-lockable device the customer lockable ve rsion allows the security sector to be freely programmed or erased and then permanently locked. note that the es29lv320 has a security sector size of 256 bytes (128 words). note that the accelerated programming (acc) and unlock bypass functions are not available when program- ming the security sector. protection of the security sector the security sector area can be protected using the following procedures: write the three-cycle ?enter security sector command? sequence, and then fol- lowing the in-system sector protect algorithm as shown in fig. 2, exce pt that reset# may be at either v ih or v id . this allows in-system protection of the security sector without raising any device pin to a high voltage. note that this method is only appli- cable to the security sect or. to verify the protect/ unprotect status of the security sector. follow the algorithm shown in fig. 2.
esi esi 11 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. exit from the security sector once the security sector is locked protected and verified, the system must write the exit security sector region command sequence to return to reading and writing the remainder of the array. caution for the security sector protection the security sector protection must be used with caution since, once protected, there is no proce- dure available for unprotecting the security sector area and none of the bits in the security sector memory space can be modified in any way. hardware data protection the es29lv320 device provides some protection measures against accidental erasure or program- ming caused by spurious system level signals that may exist during power transition. during power- up, all internal registers and latches in the device are cleared and the device automatically resets to the read mode. in addition, with its internal state machine built-in the device, any alteration of the memory contents or any initiation of new operation start reset# = v ih or v id wait 1us security sector protect verify complete remove v ih or v id from reset# if data=00h, security sector is unprotected. if data=01h, security sector is protected read from security sector address with a6=0,a1=1,a0=0 write 60h to any address write 40h to security sector address with a6=0, a1=1,a0=0 write reset command figure 2. security sector protect verify can only occur after succe ssful completion of spe- cific command sequences. and several features are incorporated to prevent inadvertent write cycles resulting from vcc power-up and power-down transi- tion or system noise. low vcc write inhibit when vcc is less than v lko , the device does not accept any write cycles. this protects data during vcc power-up and power-down. the command reg- ister and all internal program/erase circuits are dis- abled, and the device resets to the read mode. subsequent writes are ignored until vcc is greater than v lko . the system must provide proper signals to the control pins to prevent unintentional writes when vcc is greater than v lko . write pulse ?glitch? protection noise pulses of less than 5ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe#=v il , ce#=v ih or we#=v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we#=ce#=v il and oe#=v ih during power up, the device does not accept any commands on the rising edge of we#. the internal state machine is automat- ically reset to the read mode on power-up.
esi esi 12 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. operation ce# oe# we# reset# wp#/acc addresses (note 1) dq0 ~ dq7 dq8~dq15 byte# = v ih byte# = v il read l l h hl/h a in d out d out dq8~dq14 = high-z, dq15 = a-1 write l h l h (note 3) a in (note 4) (note 4) accelerated program l h l h v hh a in (note 4) (note 4) standby vcc+ 0.3v x x vcc+ 0.3v h x high-z high-z high-z output disable reset l h h h l/h x high-z high-z x x x l l/h x high-z high-z in-system sector protect (note 2) lh l v id l/h sa,a6=l, a1=h,a0=l (note 4) x x sector unprotect (note 2) l h l v id l/h (note 3) sa,a6=h, a1=h,a0=l (note 4) x x temporary sec- tor unprotect x x x v id h (note 3) a in (note 4) (note 4) high-z a9 high-volt- age method sector protect l v id l h h (note 3) sa,a9=v id , a6=l, a1=h,a0=l (note 4) (note 4) high-z sector unprotect l v id l h h (note 3) sa,a9=v id , a6=h, a1=h,a0=l table 1. es29lv320 device bus operations legend : l=logic low=v il , h=logic high=v ih , v id =11.5-12.5v, v hh =11.5-12.5v, x=don?t care, sa=sector address, a in =address in, d in =data in, d out =data out notes : 1. addresses are a20:a0 in word mode (byte#=v ih ) , a20:a-1 in byte mode (byte#=v il ). 2. the sector protect and sector unprotect functions may also be implemented via programming equipment. see the ?sector/sector block protection and unprotection? section. 3. if wp#/acc=v il , the two outermost boot sectors remain protected. if wp#/acc=v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in ?sector/sector block protection an d unprotection?. if wp#/acc=v hh , all sectors will be unprotected. 4. d in or d out as required by command sequence, data polling, or sector protection algorithm. description ce# oe# we# a20 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq8~dq15 dq7~dq0 byte# = v ih byte# = v il manufactureid:esi l l h xx v id xlxll x x4ah device id: es29lv320e llh x x v id x l x l h 22h x f6(t),f9h(b) sector protection verification llhsa x v id xlxhl x x 01h(protected) 00h(unprotected) security sector indicator bit(dq7) l l h x x v id xlxhh x x 99h(factory-locked), 19h(customer-lock- able) legend : t= top boot block, b = bottom boot block, l=logic low=v il , h=logic high=v ih , sa=sector address, x = don?t care table 2. autoselect codes (a9 high-voltage method)
esi esi 13 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 3. top boot sector addresses (es29lv320et) group sector sector address a20~a12 sector size (kbytes/kwords) (x8) address range (x16) address range remark sg0 sa0 000000xxx 64/32 000000h~00ffffh 000000h~07fffh sa1 000001xxx 64/32 010000h~01ffffh 008000h~0ffffh sa2 000010xxx 64/32 020000h~02ffffh 010000h~17fffh sa3 000011xxx 64/32 030000h~03ffffh 018000h~01ffffh sg1 sa4 000100xxx 64/32 040000h~04ffffh 020000h~027fffh sa5 000101xxx 64/32 050000h~05ffffh 028000h~02ffffh sa6 000110xxx 64/32 060000h~06ffffh 030000h~037fffh sa7 000111xxx 64/32 070000h~07ffffh 038000h~03ffffh sg2 sa8 001000xxx 64/32 080000h~08ffffh 040000h~047fffh sa9 001001xxx 64/32 090000h~09ffffh 048000h~04ffffh sa10 001010xxx 64/32 0a0000h~0affffh 050000h~057fffh sa11 001011xxx 64/32 0b0000h~0bffffh 058000h~05ffffh sg3 sa12 001100xxx 64/32 0c0000h~0cffffh 060000h~067fffh sa13 001101xxx 64/32 0d0000h~0dffffh 068000h~06ffffh sa14 001110xxx 64/32 0e0000h~0effffh 070000h~077fffh sa15 001111xxx 64/32 0f0000h~0fffffh 078000h~07ffffh sg4 sa16 010000xxx 64/32 100000h~10ffffh 080000h~087fffh sa17 010001xxx 64/32 110000h~11ffffh 088000h~08ffffh sa18 010010xxx 64/32 120000h~12ffffh 090000h~097fffh sa19 010011xxx 64/32 130000h~13ffffh 098000h~09ffffh sg5 sa20 010100xxx 64/32 140000h~14ffffh 0a0000h~0a7fffh sa21 010101xxx 64/32 150000h~15ffffh 0a8000h~0affffh sa22 010110xxx 64/32 160000h~16ffffh 0b0000h~0b7fffh sa23 010111xxx 64/32 170000h~17ffffh 0b8000h~0bffffh sg6 sa24 011000xxx 64/32 180000h~18ffffh 0c0000h~0c7fffh sa25 011001xxx 64/32 190000h~19ffffh 0c8000h~0cffffh sa26 011010xxx 64/32 1a0000h~1affffh 0d0000h~0d7fffh sa27 011011xxx 64/32 1b0000h~1bffffh 0d8000h~0dffffh sg7 sa28 011100xxx 64/32 1c0000h~1cffffh 0e0000h~0e7fffh sa29 011101xxx 64/32 1d0000h~1dffffh 0e8000h~0effffh sa30 011110xxx 64/32 1e0000h~1effffh 0f0000h~0f7fffh sa31 011111xxx 64/32 1f0000h~1fffffh 0f8000h~0fffffh sg8 sa32 100000xxx 64/32 200000h~20ffffh 100000h~107fffh sa33 100001xxx 64/32 210000h~21ffffh 108000h~10ffffh sa34 100010xxx 64/32 220000h~22ffffh 110000h~117fffh sa35 100011xxx 64/32 230000h~23ffffh 118000h~11ffffh sg9 sa36 100100xxx 64/32 240000h~24ffffh 120000h~127fffh sa37 100101xxx 64/32 250000h~25ffffh 128000h~12ffffh sa38 100110xxx 64/32 260000h~26ffffh 130000h~137fffh sa39 100111xxx 64/32 270000h~27ffffh 138000h~13ffffh sg10 sa40 101000xxx 64/32 280000h~28ffffh 140000h~147fffh sa41 101001xxx 64/32 290000h~29ffffh 148000h~14ffffh sa42 101010xxx 64/32 2a0000h~2affffh 150000h~157fffh sa43 101011xxx 64/32 2b0000h~2bffffh 158000h~15ffffh sg11 sa44 101100xxx 64/32 2c0000h~2cffffh 160000h~167fffh sa45 101101xxx 64/32 2d0000h~2dffffh 168000h~16ffffh sa46 101110xxx 64/32 2e0000h~2effffh 170000h~177fffh sa47 101111xxx 64/32 2f0000h~2fffffh 178000h~17ffffh sg12 sa48 110000xxx 64/32 300000h~30ffffh 180000h~187fffh sa49 110001xxx 64/32 310000h~31ffffh 188000h~18ffffh sa50 110010xxx 64/32 320000h~32ffffh 190000h~197fffh sa51 110011xxx 64/32 330000h~33ffffh 198000h~19ffffh sg13 sa52 110100xxx 64/32 340000h~34ffffh 1a0000h~1a7fffh sa53 110101xxx 64/32 350000h~35ffffh 1a8000h~1affffh sa54 110110xxx 64/32 360000h~36ffffh 1b0000h~1b7fffh sa55 110111xxx 64/32 370000h~37ffffh 1b8000h~1bffffh main sector
esi esi 14 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 3. top boot sector addresses (es29lv320et) continued group sector sector address a20~a12 sector size (kbytes/kwords) (x8) address range (x16) address range remark sg14 sa56 111000xxx 64/32 380000h~38ffffh 1c0000h~1c7fffh sa57 111001xxx 64/32 390000h~39ffffh 1c8000h~1cffffh sa58 111010xxx 64/32 3a0000h~3affffh 1d0000h~1d7fffh sa59 111011xxx 64/32 3b0000h~3bffffh 1d8000h~1dffffh sg15 sa60 111100xxx 64/32 3c0000h~3cffffh 1e0000h~1e7fffh sa61 111101xxx 64/32 3d0000h~3dffffh 1e8000h~1effffh sa62 111110xxx 64/32 3e0000h~3effffh 1f0000h~1f7fffh sg16 sa63 111111000 8/4 3f0000h~3f1fffh 1f8000h~1f8fffh sg17 sa64 111111001 8/4 3f2000h~3f3fffh 1f9000h~1f9fffh sg18 sa65 111111010 8/4 3f4000h~3f5fffh 1fa000h~1fafffh sg19 sa66 111111011 8/4 3f6000h~3f7fffh 1fb000h~1fbfffh sg20 sa67 111111100 8/4 3f8000h~3f9fffh 1fc000h~1fcfffh sg21 sa68 111111101 8/4 3fa000h~3fbfffh 1fd000h~1fdfffh sg22 sa69 111111110 8/4 3fc 000h~3fdfffh 1fe000h~1fefffh sg23 sa70 111111111 8/4 3fe000h~3fffffh 1ff000h~1fffffh security sector 111111111 bytes/words (256/128) 3fff00h~3fffffh 1fff80h~1fffffh note : the addresses range is a20:a-1 in byte mode (byte#=v il ) or a20:a0 in word mode (byte#=v ih ). boot sector sa69,sa70 protected at wp#/ acc=low main sector
esi esi 15 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 4. bottom boot sector addresses (es29lv320eb) group sector sector address a20~a12 sector size (kbytes/kwords) (x8) address range (x16) address range remark sg0 sa0 000000000 8/4 000000h~001fffh 000000h~000fffh sg1 sa1 000000001 8/4 002000h~003fffh 001000h~001fffh sg2 sa2 000000010 8/4 004000h~005fffh 002000h~002fffh sg3 sa3 000000011 8/4 006000h~007fffh 003000h~003fffh sg4 sa4 000000100 8/4 008000h~009fffh 004000h~004fffh sg5 sa5 000000101 8/4 00a000h~00bfffh 005000h~005fffh sg6 sa6 000000110 8/4 00c000h~00dfffh 006000h~006fffh sg7 sa7 000000111 8/4 00e000h~00ffffh 007000h~007fffh sg8 sa8 000001xxx 64/32 010000h~01ffffh 008000h~00ffffh sa9 000010xxx 64/32 020000h~02ffffh 010000h~017fffh sa10 000011xxx 64/32 030000h~03ffffh 018000h~01ffffh sg9 sa11 000100xxx 64/32 040000h~04ffffh 020000h~027fffh sa12 000101xxx 64/32 050000h~05ffffh 028000h~02ffffh sa13 000110xxx 64/32 060000h~06ffffh 030000h~037fffh sa14 000111xxx 64/32 070000h~07ffffh 038000h~03ffffh sg10 sa15 001000xxx 64/32 080000h~08ffffh 040000h~047fffh sa16 001001xxx 64/32 090000h~09ffffh 048000h~04ffffh sa17 001010xxx 64/32 0a0000h~0affffh 050000h~057fffh sa18 001011xxx 64/32 0b0000h~0bffffh 058000h~05ffffh sg11 sa19 001100xxx 64/32 0c0000h~0cffffh 060000h~067fffh sa20 001101xxx 64/32 0d0000h~0dffffh 068000h~06ffffh sa21 001110xxx 64/32 0e0000h~0effffh 070000h~077fffh sa22 001111xxx 64/32 0f0000h~0fffffh 078000h~07ffffh sg12 sa23 010000xxx 64/32 100000h~10ffffh 080000h~087fffh sa24 010001xxx 64/32 110000h~11ffffh 088000h~08ffffh sa25 010010xxx 64/32 120000h~12ffffh 090000h~097fffh sa26 010011xxx 64/32 130000h~13ffffh 098000h~09ffffh sg13 sa27 010100xxx 64/32 140000h~14ffffh 0a0000h~0a7fffh sa28 010101xxx 64/32 150000h~15ffffh 0a8000h~0affffh sa29 010110xxx 64/32 160000h~16ffffh 0b0000h~0b7fffh sa30 010111xxx 64/32 170000h~17ffffh 0b8000h~0bffffh sg14 sa31 011000xxx 64/32 180000h~18ffffh 0c0000h~0c7fffh sa32 011001xxx 64/32 190000h~19ffffh 0c8000h~0cffffh sa33 011010xxx 64/32 1a0000h~1affffh 0d0000h~0d7fffh sa34 011011xxx 64/32 1b0000h~1bffffh 0d8000h~0dffffh sg15 sa35 011100xxx 64/32 1c0000h~1cffffh 0e0000h~0e7fffh sa36 011101xxx 64/32 1d0000h~1dffffh 0e8000h~0effffh sa37 011110xxx 64/32 1e0000h~1effffh 0f0000h~0f7fffh sa38 011111xxx 64/32 1f0000h~1fffffh 0f8000h~0fffffh sg16 sa39 100000xxx 64/32 200000h~20ffffh 100000h~107fffh sa40 100001xxx 64/32 210000h~21ffffh 108000h~10ffffh sa41 100010xxx 64/32 220000h~22ffffh 110000h~117fffh sa42 100011xxx 64/32 230000h~23ffffh 118000h~11ffffh sg17 sa43 100100xxx 64/32 240000h~24ffffh 120000h~127fffh sa44 100101xxx 64/32 250000h~25ffffh 128000h~12ffffh sa45 100110xxx 64/32 260000h~26ffffh 130000h~137fffh sa46 100111xxx 64/32 270000h~27ffffh 138000h~13ffffh sg18 sa47 101000xxx 64/32 280000h~28ffffh 140000h~147fffh sa48 101001xxx 64/32 290000h~29ffffh 148000h~14ffffh sa49 101010xxx 64/32 2a0000h~2affffh 150000h~157fffh sa50 101011xxx 64/32 2b0000h~2bffffh 158000h~15ffffh sg19 sa51 101100xxx 64/32 2c0000h~2cffffh 160000h~167fffh sa52 101101xxx 64/32 2d0000h~2dffffh 168000h~16ffffh sa53 101110xxx 64/32 2e0000h~2effffh 170000h~177fffh sa54 101111xxx 64/32 2f0000h~2fffffh 178000h~17ffffh boot sector sa0,sa1 protected at wp#/ acc=low main sector
esi esi 16 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 4. bottom boot sector addresses (es29lv320eb) continued group sector sector address a20~a12 sector size (kbytes/kwords) (x8) address range (x16) address range remark sg20 sa55 110000xxx 64/32 300000h~30ffffh 180000h~187fffh sa56 110001xxx 64/32 310000h~31ffffh 188000h~18ffffh sa57 110010xxx 64/32 320000h~32ffffh 190000h~197fffh sa58 110011xxx 64/32 330000h~33ffffh 198000h~19ffffh sg21 sa59 110100xxx 64/32 340000h~34ffffh 1a0000h~1a7fffh sa60 110101xxx 64/32 350000h~35ffffh 1a8000h~1affffh sa61 110110xxx 64/32 360000h~36ffffh 1b0000h~1b7fffh sa62 110111xxx 64/32 370000h~37ffffh 1b8000h~1bffffh sg22 sa63 111000xxx 64/32 380000h~38ffffh 1c0000h~1c7fffh sa64 111001xxx 64/32 390000h~39ffffh 1c8000h~1cffffh sa65 111010xxx 64/32 3a0000h~3affffh 1d0000h~1d7fffh sa66 111011xxx 64/32 3b0000h~3bffffh 1d8000h~1dffffh sg23 sa67 111100xxx 64/32 3c0000h~3cffffh 1e0000h~1e7fffh sa68 111101xxx 64/32 3d0000h~3dffffh 1e8000h~1effffh sa69 111110xxx 64/32 3e0000h~3effffh 1f0000h~1f7fffh sa70 111111xxx 64/32 3f0000h~3fffffh 1f8000h~1fffffh security sector 000000000 bytes/words (256/128) 000000h~0000ffh 000000h~00007fh note : the addresses range is a20:a-1 in byte mode (byte#=v il ) or a20:a0 in word mode (byte#=v ih ). main sector
esi esi 17 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. start reset# = v id set up sector address count = 1 wait 1us first write cycle = 60h? sector protect: write 60h to sec- tor address with a6 = 0, a1 = 1, a0 = 0 wait 150us verify sector protect: write 40h to sec- tor address with a6 = 0, a1 = 1, a0 = 0 data = 01h? protect another sector? remove v id from reset# write reset command sector protect complete temporary sector unprotect mode no count=25? increment count read from sec- tor address with a6 = 0, a1 = 1, a0 = 0 device failed no yes yes no no reset count = 1 yes figure 3. in-system sector protect algorithm yes start reset# = v id set up first sector address count = 1 wait 1us first write cycle = 60h? sector unpro- tect: write 60h to sec- tor address with a6 = 1, a1 = 1, wait 15ms verify sector unprotect: write 40h to sec- tor address with a6 = 1, a1 = 1, a0 = 0 data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete temporary sector unprotect mode no count =1000? increment count read from sec- tor address with a6 = 1, a1 = 1, a0 = 0 device failed no yes yes no no set up next sector address ye s ye s all sectors protected ? protect all sectors: the indicated por- tion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address no ye s figure 4. in-system sector unprotect algorithm in-system protection / unprotection method
esi esi 18 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. no yes yes no set a9=oe#=v id remove v id from a9 and write reset command sector protection complete set sector address a<20 :12> ce#, a6, a0=v il reset#, a1=v ih protect another sector ? read data data = 01h? ce#,oe#,a6,a0=v il reset#, a1 = v ih set we# = v il start count = 1 wait 150 us set we# = v ih increase count count= 25? device failed yes no no yes yes no set a9=oe#=v id remove v id from a9 and write reset command sector unprotection complete set sector addressa<20 :12> read data set we# = v il count = 1 set we# = v ih start note: all sectors must be previously protected. wait 15ms ce#,oe#, a0=v il reset#, a6, a1=v ih data = 00h? the last sector address ? yes no increase sector address increase count device failed count=1000? ce#, a0=v il , reset#, a6, a1=v ih figure 6. sector un-protection algorithm (a9 high-voltage method) figure 5. sector protection algorithm (a9 high-voltage method) a9 high-voltage method
esi esi 19 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 5. cfi query identification string addresses (word mode) addresses (byte mode) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set(00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) cfi is supported in the es29lv320 device. the common flash interface (cfi) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. software support can then be device-inde- pendent, jedec id-independent, and forward- and backward-compatible for the specified flash device families. flash vendors ca n standardize their exist- ing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command , 98h, to address 55h in word mode (or address aah in byte mode), any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 5-8. to terminate reading cfi data, the system must write the reset com- mand .the cfi query command can be written to the system when the device is in the autoselect mode or the erase-suspend-read mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 5-8. when the reset command is written, the device returns respectively to the read mode or erase-sus- pend-read mode. table 6. system interface string addresses (word mode) addresses (byte mode) data description 1bh 36h 0027h vcc min. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1ch 38h 0036h vcc max. (write/erase) d7-d4: volt, d3-d0: 100 millivolt 1dh 3ah 0000h vpp min. voltage (00h = no vpp pin present) 1eh 3ch 0000h vpp max. voltage (00h = no vpp pin present) 1fh 3eh 0004h typical timeout per si ngle byte/word write 2 n us 20h 40h 0000h typical timeout for min. size buffer write 2 n us (00h = not supported) 21h 42h 000ah typical timeout per indi vidual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0005h max. timeout for byte/word write 2 n times typical 24h 48h 0000h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per indivi dual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported) common flash memory interface (cfi)
esi esi 20 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 7. device geometry definition addresses (word mode) addresses (byte mode) data description 27h 4eh 0016h device size = 2 n byte 28h 29h 50h 52h 0002h 0000h flash device interface description 02 = x8, x16 asynchronous 2ah 2bh 54h 56h 0000h 0000h max. number of bytes multi-byte write = 2 n (00h = not supported) 2ch 58h 0002h number of erase block regions within device 2dh 2eh 5ah 5ch 0007h 0000h erase block region 1 information number of identical size erase block = 0007h+1 =8 2fh 30h 5eh 60h 0020h 0000h erase block region 1 information number of identical size eras e block = 0020h * 256byte = 8kbyte 31h 32h 62h 64h 003eh 0000h erase block region 2 information number of identical size erase block = 003eh+1 =63 33h 34h 66h 68h 0000h 0001h erase block region 2 information number of identical size eras e block = 0100h * 256byte = 64kbyte 35h 36h 6ah 6ch 0000h 0000h erase block region 3 information 37h 38h 6eh 70h 0000h 0000h erase block region 3 information 39h 3ah 72h 74h 0000h 0000h erase block region 4 information 3bh 3ch 76h 78h 0000h 0000h erase block region 4 information
esi esi 21 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 8. primary vendor-specific extended query addresses (word mode) addresses (byte mode) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0031h minor version number, ascii 45h 8ah 0000h address sensitive unlock (bits 1-0) 0 = required, 1 = not required silicon revision number (bits 7-2) 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0004h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0001h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/u nprotect scheme 04 = in-system method and a9 high-voltage method 4ah 94h 0000h simultaneous operation 00 = not supported 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0000h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc(acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100mv 4eh 9ch 00c5h acc(acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100mv 4fh 9eh 000xh top/bottom boot sector flag 02h = bottom boot device, 03h = top boot device
esi esi 22 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. writing specific address and data commands or sequences into the command register initiates device operations. table 9 defines the valid register command sequences. note that writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset command is required to return the device to normal operation. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever hap- pens first. refer to the ac characteristics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend com- mand, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see the erase suspend/erase resume commands sectio n for more information. the system must issue t he reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next sectio n, reset command, for more information. see also requirements for reading array data in the device bus operations section for more informa- tion.the read-only operati ons table provides the read parameters, and fig. 18 shows the timing dia- gram reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to which the system was writ ing to the read mode. once erasure begins, how ever, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to which the system was writing to the read mode. if the program command sequence is written to a sec- tor that is in the erase suspend mode, writing the reset command returns the device to the erase-sus- pend-read mode. once programming begins, how- ever, the device ignore s reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend- read mode. if dq5 goes high during a program or erase opera- tion, writing the reset comm and returns the device to the read mode (or erase-suspend-read mode if the device was in erase-suspend). command definitions
esi esi 23 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. table 9. es29lv320 command definitions command definitions command sequence (note 1) cycles bus cycles (notes 2~5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id word 4 555 aa 2aa 55 555 90 x00 4a byte aaa 555 aaa device id word 4 555 aa 2aa 55 555 90 x01 (see table 2) byte aaa 555 aaa x02 security sector fac tory protect (note 9) word 4 555 aa 2aa 55 555 90 x03 99/19 byte aaa 555 aaa x06 sector protect verify (note 10) word 4 555 aa 2aa 55 555 90 (sa)x02 00/01 byte aaa 555 aaa (sa)x04 enter security sector region word 3 555 aa 2aa 55 555 88 byte aaa 555 aaa exit security sector region word 4 555 aa 2aa 55 555 90 xxx 00 byte aaa 555 aaa program word 4 555 aa 2aa 55 555 a0 pa pd byte aaa 555 aaa unlock bypass word 3 555 aa 2aa 55 555 20 byte aaa 555 aaa unlock bypass program (note 11) 2 xxx a0 pa pd unlock bypass reset (note 12) 2 xxx 90 xxx 00 chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte aaa 555 aaa aaa 555 aaa sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte aaa 555 aaa aaa 555 erase suspend (note 13) 1 xxx b0 erase resume (note 14) 1 xxx 30 cfi query (note 15) word 1 55 98 byte aa legend: x = don?t care ra = address of the memory location to be read. rd = data read from loc ation ra during read operation pa = address of the memory location to be programmed. addresses latch on the falling edge of the we# or ce# pulse, whichever happens later. pd = data to be programmed at location pa. data latches on the rising edge of we# or ce# pul se, whichever happens first. sa = address of the sector to be verified (in autoselect mode) or erased. address bits a20-a12 uniquely select any sector. 9. the data is 99h for factory locked and 19h for not factory locked. 10. the data is 00h for an unprotected sector and 01h for a protected sector. 11. the unlock bypass command is required prior to the unlock- bypass program command. 12. the unlock bypass reset command is required to return to the read mode when the device is in the unlock bypass mode. 13. the system may read and progr am in non-erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 14. the erase resume command is valid only during the erase suspend mode. 15. command is valid when device is ready to read array data or when device is in autoselect mode. notes: 1. see table 1 for descr iption of bus operations. 2. all values are in hexadecimal. 3. except for the read cycle and the fourth cycle of the autoselect command sequence, all bus cycles are write cycles. 4. data bits dq15-dq8 are don ?t care in command sequences, except for rd and pd 5. unless otherwise noted, address bits a20-a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. the reset command is requi red to return to the read mode (or to the erase-suspend-r ead mode if previously in erase suspend) when a device is in the autoselect mode, or if dq5 goes high (while the device is providing status information). 8. the fourth cycle of the autoselect command sequence is a read cycle. data bits dq15-dq8 are don?t care. see the autoselect command sequence section for more information.
esi esi 24 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. autoselect command the autoselect command se quence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected, including information about factory- locked or customer lockable version. table 9 shows the address and data requirements. this method is an alternative to ?a9 high-voltage method? shown in table 2, which is intended for prom programmers and requires v id on address pin a9. the autoselect command sequence may be written to an address within sector that is either in the read mode or erase-suspend-read mode. the auto-select command may not be written while the device is actively programming or erasing. the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect com- mand sequence. once after the device enters the auto-select mode, the manufacture id code ( 4ah ) can be accessed by one of two ways. just one read cycle ( with a6, a1 and a0 = 0 ) can be used. or four consecutive read cycles ( with a6 = 1 and a1, a0 = 0 ) for con- tinuation codes (7fh) and then another last cycle for the code (4ah) (with a6, a1 and a0 = 0) can be used for reading the manufacturer code. - 4ah (one-cycle read) - 7fh 7fh 7fh 7fh 4ah (five-cycle read) the system must write the reset command to return to the read mode (or erase-suspend-read mode if the device was previously in erase suspend). identifier code address data manufacturer id 00h 4ah device id 01h f6(t), f9h(b) security sector factory protect 03h 99 / 19 sector group protect verify (sa)02h 00 / 01 security sector command in the es29lv320 device, t he security sector region (256 bytes) provides a secured data area containing a random, sixteen-byte electronic serial num- ber(esn) or customer?s security codes. the secu- rity sector region can be accessed by issuing the three-cycle enter security sector command sequence. the device continues to access the security sector region until the system issues the four-cycle exit security sector command sequence. the exit security sector command sequence returns the device to normal operation. table 9 shows the address and data requirements for both command sequences. note that the accel- erated programming function by wp#acc and unlock bypass mode are not available when the device has entered the securi ty sector. refer to the fig. 7 for the security sector operation. read mode enter security sector command program, erase or protection exit security sector command read mode figure 7 . security sector operation
esi esi 25 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. byte / word program the system may program the device by word or byte, depending on the state of the byte# pin . programming is a four-bus-cycle operation. the program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device auto- matically provides internally generated program pulses and verifies the programmed cell margin. table 9 shows the address and data requirements for the byte program command sequence. note that the autoselect, commands re lated with the security sector, and cfi modes are unavailable while a pro- gramming operation is in progress. program status bits : dq7, dq6 or ry/by# when the embedded program algorithm is com- plete, the device then returns to the read mode and addresses are no longer latched. the system can determine the status of the program operation by using dq7, dq6, or ry/ by#. refer to the write operation status section table 10 for information on these status bits. any commands ignored during program- ming operation any commands written to the device during the embedded program algorithm are ignored. note that a hardware reset can immediately terminates the program operation. the program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. programming from ?0? back to ?1? programming is allowed in any sequence and across sector boundaries. but a bit cannot be pro- grammed from ?0? back to a ?1?. attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was successful. however, a succeeding read will show that the data is still ?0?. only erase operations can convert a ?0? to a ?1? unlock bypass in the es29lv320 device, an unlock bypass pro- gram mode is provided for faster programming oper- ation. in this mode, two cycles of program command sequences can be saved. to enter this mode, an unlock bypass enter command should be first written to the system. the unlock bypass enter command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle contain- ing the unlock bypass command, 20h. the device then enters the unlock-bypass program mode. a two-cycle unlock bypass program command sequence is all that is required to program in this mode. the first cycle in this sequence contains the unlock bypass program set-up command, a0h; the second cycle contains t he program address and data. additional data is programmed in the same manner. this mode dispen ses with the initial two unlock cycles required in the standard program com- mand sequence, resulting in faster total program- ming time. table 9 shows the requirements for the command sequence. start verify data ? increment address write program com- mand sequence data poll from system last address? yes programming completed embedded program algorithm in progress no no ye s note: see table 9 for program command sequence figure 8. program operation
esi esi 26 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. during the unlock-bypass mode, only the unlock- bypass program and unlo ck-bypass reset com- mands are valid. to exit the unlock-bypass mode, the system must issue the two-cycle unlock-bypass reset command sequence. the first cycle must con- tain the data 90h. the second cycle need to only contain the data 00h. the device then returns to the read mode. - unlock bypass enter command - unlock bypass reset command - unlock bypass program command unlock bypass program during wp#/acc accelerated program mode the device offers accelerated program operations through the wp#/acc pin. when the system asserts v hh on the wp#/acc pin, the device auto- matically enters the unlock bypass mode. the sys- tem may then write the two-cycle unlock bypass program command sequence. the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/acc pin must not be at v hh in any operation other than accelerated programming, or device damage may result. in addition, the wp#/acc pin must not be left floating or unconnected; inconsiste nt behavior of the device may result. fig. 8 illustra tes the algorithm for the program operation. refer to the erase and program operations table in the ac characteristics section for parameters, and fig. 22 for timing diagrams. chip erase command to erase the entire memory, a chip erase command is used. this command is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up com- mand. two additional unlo ck write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the chip erase command erases the entire memory includ- ing all other sectors except the protected sectors, but the internal erase operation is performed on a single sector base. embedded erase algorithm the device does not require the system to prepro- gram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to pro- vide any controls or ti mings during these opera- tions. table 9 shows the address and data requirements for the chip erase command sequence. note that the autoselect, security sector, and cfi modes are unavailable while an erase operation is in progress erase status bits : dq7, dq6, dq2, or ry/by# when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. th e system can determine the status of the erase operation by using dq7, dq6, dq2, or ry/by#. refer to the write operation status section table 10 for inform ation on these status bits. commands ignored during erase operation any command written during the chip erase opera- tion are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data. to ensure data in tegrity. fig. 9 illustrates the algorithm for the erase operation. refer to the erase and program operations tables in the ac characteristics section fo r parameters, and fig. 23 section for timing diagrams. sector erase command by using a sector erase command, a single sector or multiple sectors can be erased. the sector erase command is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. table 9 shows the address and data requirements for the sector erase command sequence. note th at the autoselect, secu- rity sector, and cfi modes are unavailable while an erase operation is in progress. embedded sector erase algorithm the device does not require the system to prepro- gram prior to erase. the embedded erase algorithm automatically programs and verifies the entire mem- ory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings these operations.
esi esi 27 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. sector erase time-out window and dq3 after the command sequence is written, a sector erase time-out of 50us occurs. during the time-out period, additional sector addresses and sector erase commands may be written. loading the sec- tor erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50us, otherwise the last address and command may not be accepted, and erasure may begin. it is recommended that processor inter- rupts be disabled during this time to ensure all com- mands are accepted. the interrupts can be re- enabled after the last sector erase command is written. the system can monitor dq3 to determine if the sector erase timer has timed out (see the sec- tion on dq3:sector erase timer.). the time-out begins from the rising edge of the final we# pulse in the command sequence. any command other than sector erase or erase suspend during the time-out period resets the device to the read mode. the system must rewrite the command sequence and any additional addresses and commands. status bits : dq7,dq6,dq2, or ry/by# when the sector erase embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. note that while the embedded erase operation is in progress, the system can read data from the non-erasing sector. the system can determine the status of the erase operation by reading dq7,dq6,dq2, or ry/by# in the erasing sector. refer to the write operation sta- tus section table 10 for information on these status bits. valid command during sector erase once the sector erase operation has begun, only the erase suspend command is valid. all other com- mands are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. fig. 9 illustrates the algor ithm for the erase opera- tion. refer to the erase and program operations tables in the ac characteristics section for parame- ters, and fig. 23 section for timing diagrams. erase suspend/ erase resume an erase operation is a long-time operation so that two useful commands are provided in the es29lv320 device erase suspend and erase resume commands. through the two commands, erase operation can be suspended for a while and the suspended operation can be resumed later when it is required. while the erase is suspended, read or program operations can be performed by the system. erase suspend command, (b0h) the erase suspend command, b0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only dur- ing the sector erase operation, including the 50us time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embed- ded program algorithm. when the erase suspend command is written during the sector erase opera- tion, the device requires a maximum of 20us to sus- pend the erase operation. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time- out period and suspends the erase operation. figure 9. erase operation notes: 1. see table 9 for erase command sequence 2. see the section on dq3 for inform ation on the sector erase timer start no yes write erase command sequence (notes 1,2) data poll to erasing bank from system data = ffh? erasure completed embedded erase algorithm in progress
esi esi 28 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. read and program during erase-suspend- read mode after the erase operation has been suspended, the device enters the erase-suspend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors pro- duces status information on dq7-dq0. the system can use dq7, or dq6 and dq2 together, to deter- mine if a sector is actively erasing or is erase-sus- pended. refer to the write operation status section for information on these status bits (table 10). after an erase-suspended program operation is complete, the device returns to the erase-suspend- read mode. the system can determine the status for the program operation usin g the dq7 or dq6 status bits, just as in the standard byte program operation. refer to the write operation status section for more information. autoselect during erase-suspend- read mode in the erase-suspend-read mode, the system can also issue the autoselected command sequence. refer to the autoselect mode and autoselect com- mand sequence section for details (table 9). erase resume command to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
esi esi 29 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. program unlock bypass auto- select cfi read security sector chip erase sector erase erase- suspend read pa/pd a0 20 90 00 98 f0 f0 98 resume 30 b0 suspend 50us sa/30 sa/30 10 55 aa 80 88 55 aa 00 done 90 55 aa 90 command diagram figure 10. command diagram done done
esi esi 30 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. in the es29lv320 device, several bits are provided to determine the status of a program or erase oper- ation: dq2, dq3, dq5, dq6, dq7 and ry/by#. table 10 and the following subsections describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/ by#, to determine whether an embedded program or erase operation is in progress or has been com- pleted. dq7 (data# polling) the data# polling bit, dq7, indicates to the host system whether an embedde d program or erase algorithm is in progress or completed, or whether a device is in erase sus pend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during programming during the embedded program algorithm, the device outputs on dq7 the complement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is com- plete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector , data# polling on dq7 is active for approximately 250ns , then the device returns to the read mode. during erase during the embedded erase algorithm, data# poll- ing produces a ?0? on dq7 . when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors se lected for erasure to read valid status information on dq7. erase on the protected sectors after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is acti ve for approximately 1.8us , then the device returns to the read mode. if not all selected sectors are prot ected, the embedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. how- ever, if the system reads dq7 at an address within a protected sector, the status may not be valid. data# polling algorithm just prior to the completion of an embedded program or ease operation, dq7 may change asynchronously with dq0-dq6 while output enable(oe#) is asserted low. that is, this device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0-dq7 will appear on successive read cycles. table 10 shows the outputs for data# polling on dq7. fig. 11 shows the da ta# polling algorithm. fig. 24 in the ac characteristics section shows the data# polling timing diagram. write operation status
esi esi 31 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ry/by# ( ready/busy# ) the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open- drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc. if the output is low (busy), the device is actively eras- ing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. table 10 shows the outputs for ry/by#. dq6 ( toggle bit i ) toggle bit i on dq6 indicates whether an embed- ded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence ( prior to the program or erase operation), and during the sec- tor erase time-out. during an embedded program or erase algorithm operation, successive read cycles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops tog- gling. the system can use dq6 and dq2 together to determine whether a sector is actively erasing or is erase-suspended. when the device is actively eras- ing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. how- ever, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7(see the sub- section on dq7:data# polling). dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. table 10 shows the outputs for toggle bit i on dq6. fig. 12 shows the toggle bi t algorithm. fig. 25 in the ?ac characteristics? section shows the toggle bit timing diagrams. fig. 26 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2 : (toggle bit ii). toggling on the protected sectors after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 1.8us , then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. if a program address falls within a protected sector, dq6 toggles for approximately 250ns after the program command sequence is writ- ten, then returns to reading array data. dq2 ( toggle bit ii ) the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively eras- ing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-sus- pended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence dq2 start no read dq7-dq0 addr = va dq7 = data ? no yes fail dq5 = 1 ? read dq7-dq0 addr = va dq7 = data ? yes pass yes no notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. duri ng chip erase, a valid address in any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5 figure 11. data# polling algorithm
esi esi 32 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. start no read dq7-dq0 toggle bit = toggle ? no yes program/erase operation not complete, write reset command dq5 = 1 ? read dq7-dq0 twice yes yes no read dq7-dq0 toggle bit = toggle ? program/erase operation complete note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1?. see the subsections on dq6 an d dq2 for more information. toggles when the system reads at addresses within those sectors that have been selected for erasure . (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase- suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 10 to compare outputs for dq2 and dq6. fig. 12 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the dq6: toggle bit i subsec- tion. fig. 25 shows the toggle bit timing diagram. fig. 26 shows how differently dq2 operates com- pared with dq6. reading toggle bits dq6/dq2 refer to fig. 12 for the following discussion. when- ever the system initially begins reading toggle bit status, it must read dq7-dq0 at least twice in a row to determine whether a toggle bit is toggling. typi- cally, the system would note and store the value of the toggle bit after the fi rst read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7-dq0 on the following read cycle. however, if after the initial two read cycles, the system deter- mines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped tog- gling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully com- pleted the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially deter- mines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the stat us as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, this sys- tem must start at the beginning of the algorithm when it returns to determine the status of the opera- tion (top of fig. 12). figure 12. toggle bit algorithm
esi esi 33 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. if additional sectors are selected for erasure, the entire time-out also app lies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a?1?. if the time between additional sector erase commands from the system can be assumed to be less than 50us , the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command se quence, and then read dq3. if dq3 is ?1?, the embedded erase algorithm has begun; all further commands (except erase sus- pend) are ignored until the erasure operation is com- plete. if dq3 is ?0?, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. in table 10, dq3 status operation is well defined and summarized with other status bits, dq7, dq6, dq5, and dq2. dq5 ( exceeded timing limits ) dq5 indicates whether the program or erase time has exceeded a specified in ternal pulse count limit. under these conditions dq5 produces a ?1?, indi- cating that the program or erase cycle was not suc- cessfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0? only an erase operation can change a ?0? back to a ?1?. under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1?. under both these conditions, the system must write th e reset command to return to the read mode. dq3 ( sector erase timer ) after writing a sector erase command sequence, the system may read dq3 to determine whether or not erasure has begun. (the sector erase time does not apply to the chip erase command.) table 10. write operation status notes : 1. dq5 switches to ?1? when an embedded program or embedded er ase operation has exceeded the maxi mum timing limits. refer to th e section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details . status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) ry/ by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 embedded erase algorithm 0 toggle 0 1 toggle 0 erase sus- pend mode erase-suspend- read erase suspended sector 1 no toggle 0 n/a toggle 1 non-erase suspended sector data data data data data 1 erase-suspend-program dq7# toggle 0 n/a n/a 0
esi esi 34 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. 20ns 20ns +0.8v vss-0.5v vss-2.0v 20ns 20ns 20ns 20ns 2.0v vcc+0.5v vcc+2.0v negative overshoot positive overshoot absolute maximum ratings storage temperature plastic packages ..............................................-65 o c to +150 o c ambient temperature with power applied ...........................................-65 o c to +125 o c voltage with respect to ground vcc (note 1) ..........................................................-0.5v to +4.0v a9, oe#, reset# and wp#/acc (note 2) ......-0.5v to +12.5v all other pins (note 1) ...................................-0.5v to vcc + 0.5v output short ci rcuit current (note 3) ................. 200ma notes: 1. minimum dc voltage on input or i/o pins is -0.5v. during voltage transitions, input or i/o pins may overshoot vss to -2.0v for per- iods of up to 20ns. maximum dc voltage on input or i/o pins is vcc+0.5v. see fig. 13. during voltage transition, input or i/o pins may overshoot to vcc+2.0v for periods up to 20ns. see fig. 13. 2. minimum dc input voltage on pins a9, oe#, reset#, and wp# /acc is -0.5v. during voltage transitions, a9, oe#, wp#/acc, and reset# may overshoot vss to -2.0v for periods of up to 20ns. see fig. 13. maximum dc input voltage on pin a9 is +12.5v which may overshoot to +14.0v for periods up to 20ns. maximum dc input voltage on wp#/acc is +9.5v which may overshoot to +12.0v for periods up to 20ns. 3. no more than one output may be shorted to ground at a time. du- ration of the short circuit should not be greater than one second. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions ab- ove those indicated in the operational sections of this datasheet is not implied. exposure of the device to absolute maximum rating con- ditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ).................................-40 o c to +85 o c commercial devices ambient temperature (t a )....................................0 o c to +70 o c vcc supply voltages vcc for all devices ............................................2.7v to 3.6v operating ranges define those limits between which the functio- nality of the device is guaranteed. figure 13. maximum overshoot waveform
esi esi 35 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. dc characteristics table 11. cmos compatible parameter symbol parameter description test conditions min typ max unit i li input load current v in =vss to vcc vcc=vcc max + 1.0 ua i lit a9 input load current vcc=vcc max; a9=12.5v 35 ua i lr reset# input load current vcc=vcc max; reset#=12.5v 35 ua i lo output leakage current vout=vss to vcc, vcc=vcc max + 1.0 ua i cci vcc active read current (notes 1,2) ce#=v il oe#=v ih , byte mode 5mhz 10 16 ma 1mhz 2 4 ce#=v il , oe#=v ih , word mode 5mhz 10 16 1mhz 2 4 i cc2 vcc active write current (note 2,3) ce#=v il , oe#=v ih , we#=v il 15 30 ma i cc3 vcc standby current (note 2) ce#, reset#= vcc+ 0.3v 15 50 ua i cc4 vcc reset current (note 2) reset#=vss + 0.3v 15 50 ua i cc5 automatic sleep mode (notes2,4) v ih = vcc + 0.3v v il = vss + 0.3v 15 50 ua v il input low voltage -0.5 0.8 v v ih input high voltage 0.7xvcc vcc+0.3 v v hh voltage for wp#/acc sector protect/unprotect and program acceleration vcc = 3.0v + 10% 11.5 12.5 v v id voltage for autoselect and temporary sector unprotect vcc = 3.0v + 10% 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, vcc = vcc min 0.45 v v oh1 output high voltage i oh = -2.0ma, vcc = vcc min 0.85 vcc v v oh2 i oh = -100 ua, vcc = vcc min vcc - 0.4 v lko low vcc lock-out voltage (note 5) 2.0 2.5 v notes: 1. the icc current listed is typically less than 2 ma/mhz, with oe# at v ih , typical condition : 25 o c, vcc = 3v 2. maximum i cc specifications are tes ted with vcc = vcc max. 3. icc active while embedded erase or embedded program is in progress. 4. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30ns. typical sleep mode current is 15 ua. 5. not 100% tested.
esi esi 36 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. dc characteristics zero-power flash figure 14. i cc1 current vs. time (showing active and automatic sleep currents) 0 500 1000 1500 2000 2500 3000 3500 4000 5 10 15 20 25 time in ns supply current in ma icc1 (active read current) icc5 (automatic sleep mode) 12 10 8 6 4 2 0 1 2 3 45 frequency in mhz supply current in ma 2.7v 3.6v figure 15. typical i cc1 vs. frequency note : addresses are switching at 1 mhz note : t = 25 o c
esi esi 37 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. test condition 70 90 output load 1ttl gate output load capacitance, c l (including jig capacitance) 30 pf 100pf input rise and fall times 5ns input pulse levels 0.0v ~ 3.0 v input timing measurement reference levels 1.5v output timing measurem ent reference levels 1.5v table 12. test specifications key to switching waveforms device under te s t 3.3v 2.7k c l ? 6.2k ? waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) figure 16. test setup note : diodes are in3064 or equivalent measurement level output input 3.0v 0.0v 1.5v 1.5v figure 17. input waveforms and measurement levels
esi esi 38 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ac characteristics table 13. read-only operations parameter description test setup speed options unit jedec std. 70 90 t avav t rc read cycle time(note 1) min 70 90 ns t avqv t acc address to output delay ce#,oe#=v il max 70 90 ns t elqv t ce chip enable to output delay oe#=v il max 70 90 ns t glqv t oe output enable to output delay max 30 40 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns note : 1. not 100% tested a ddress oe# we# outputs t rc address stable high-z output valid ce# t oeh t oh t df reset# ry/by# 0v t acc t rh t rh t ce t oe figure 18. read operation timings high-z
esi esi 39 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ce#,oe# reset# ry/by# 0v t ready t rp t rh ce#,oe# reset# ry/by# t ready t rp t rb figure 19. reset timings (b) during embedded algorithm (a) not during embedded algorithm ac characteristics table 14. hardware reset ( reset #) parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 us t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 us t rb ry/by# recovery time min 0 ns note : not 100% tested
esi esi 40 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. address input ce# byte# t fhqv dq15 output data output (dq0-dq7 ) data output (dq0-dq7) data output (dq0-dq14) address input dq15 output data output (dq0-dq14) t flqz t elfl t elfh oe# dq 15/a-1 byte# dq 0-dq14 dq 15/a-1 byte# switching switching from word to byte mode the falling edge of the last we# signal ce# byte# we# t set (t as ) t hold (t ah ) figure 21. byte# timing for write operations figure 20. byte# timing for read operations ac characteristics table 15. word/byte configuration (byte#) note : refer to the erase/program operations table for t as and t ah specifications. parameter description 70 90 unit jedec std. t elfl /t elfh ce# to byte# switching low or high max 5 ns t flqz byte# switching low to output high z max 30 ns t fhqv byte# switching high to output active min 70 90 ns byte# switching switching from byte to word mode dq 0-dq14
esi esi 41 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ac characteristics table 16. erase and program operations parameter description 70 90 unit jedec std. t avav t wc write cycle time (note 1) min 70 90 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low dur ing toggle bit polling min 15 ns t wlax t ah address hold time min 45 45 ns t aht address hold time from ce# or oe # high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 45 ns t whdx t dh data hold time min 0 ns t oeph output enable high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 30 35 ns t whdl t wph write pulse width high min 30 ns t sr/w latency between read and write operations min 0 ns t whwh1 t whwh1 programming operation (note 2) byte typ 6 us word typ 8 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 us t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs vcc setup time (note 1) min 50 us t rb write recovery time from ry/by# min 0 ns t busy program/erase valid to ry/by# delay max 90 ns notes: 1. not 100% tested. 2. see the ?erase and programming perfor mance? section for more information.
esi esi 42 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. notes : 1. pa = program address, pd = program data, dout is the true data at the program address. 2. illustration shows device in word mode. a ddress oe# we# data 555h ce# vcc ry/by# t wc program command sequence (last two cycles) pa pa pa t as t vcs t busy t whwh1 status dout a0h pd t wp t cs t wph t rb t ch read status data(last two cycles) t ds t dh figure 22. program operation timings ac characteristics t ah
esi esi 43 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. a ddress oe# we# data 2aah ce# vcc ry/by# t wc erase command sequence (last two cycles) va sa va t as t vcs t busy t whwh2 in progress complete 55h 30h t wp t cs t wph t rb t ch read status data 555h for chip erase 10h for chip erase t ds t dh notes : 1. sa = sector address(for se ctor erase), va = valid addre ss for reading status data(s ee ?write operation status?). 2. these waveforms are for the word mode. figure 23. chip/sector erase operation timings ac characteristics t ah
esi esi 44 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. a ddress oe# we# dq0-dq6 ce# ry/by# t rc figure 24. data# polling timings (during embedded algorithms) va va va t busy high-z valid data t ch t acc t ce t oh t df t oe t oeh true complement status data complement status data true valid data high-z dq7 note : va = valid address. illustration shows fi rst status cycle after command sequence, last status read cycle, and array data read c ycle ac characteristics
esi esi 45 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. a ddress oe# we# dq6/dq2 ce# ry/by# figure 25. toggle bit timings (during embedded algorithms) t oeph t dh t aht t aso t oeh valid status valid status valid status valid data valid data t ceph t aht t as t oe (first read) (second read) (stops toggling) note : va = valid address; not required for dq6. illustration shows fi rst two status cycle after command sequence, last status read cycle, and array data read cycle. dq6 we# enter embedded erasing dq2 enter suspend erase erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete figure 26. dq2 vs. dq6 note : dq2 toggles only when read at an address within an erase- suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. ac characteristics
esi esi 46 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ce# reset# ry/by# t rsp figure 27. temporary sector unprotect timing diagram t vidr program or erase command sequence t vidr t rrb v id vss,v il , or v ih wp#/acc t vhh t vhh v hh v il or v ih figure 28. accelerated program timing diagram we# parameter description all speed options unit jedec std. t vidr v id rise and fall time (see note) min 500 ns t vhh v hh rise and fall time (see note) min 250 ns t rsp reset# setup time for temporary sector unprotect min 4 us t rrb reset# hold time from ry/by# high for temporary sector unprotect min 4 us ac characteristics table 17. temporar y sector unprotect note: not 100% tested. v il or v ih
esi esi 47 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. oe# we# ce# valid* 60h 40h sector/sector group protect : 150us, sector/sector group unprotect: 15ms v id figure 29. sector/sector group protect & unprotect timing diagram 60h valid* valid* status sector/sector group protect or unprotect v ih reset# 1us sa,a6, a1,a0 dq * for sector protect, a6=0,a1=1,a0=0 fo r sector unprotect, a6=1,a1=1,a0=0 ac characteristics verify
esi esi 48 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ac characteristics table 18. alternate ce# controlle d erase and program operations parameter description 70 90 unit jedec std. t avav t wc write cycle time( note 1) min 70 90 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 45 ns t dveh t ds data setup time min 35 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 30 35 ns t elel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) byte typ 5 us word typ 7 t whwh1 t whwh1 accelerated programming operation, word or byte (note 2) typ 4 us t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec notes : 1. not 100% tested 2. see the ?erase and programming perfor mance? section for more information.
esi esi 49 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. a ddress oe# we# reset# ce# ry/by# t wc figure 30. alternate ce# controlled write(erase/program) operation timings t busy dq7# t ah t as t wh t rh t whwh1 or 2 t ws t ghel a0 for program 55 for erase data d out pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pd for program sa for sector erase 555 for chip erase pa t cp t cph t ds t dh notes : 1. figure indicates last two bus cycl es of a program or erase operation. 2. pa = program address, sa = sector address, pd = program data 3. dq7# is the complement of the data written to the device. dout is the data written to the device. 4. waveforms are for the word mode. ac characteristics data polling
esi esi 50 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. a <20:12> oe# we# reset# ce# vcc figure 31. sector protection timings (a9 high-voltage method) t wpp1 0x01 t st dq sax t oe say t oesp t csp t st t vidr t vidr a <0> a <1> a <6> a <9> v id v id table 19. ac characteristics parameter description value unit t oe output enable to output delay max 30 40 ns t vidr voltage transition time min 500 ns t wpp1 write pulse width for pr otection operation min 150 us t wpp2 write pulse width for unprotection operation min 15 ms t oesp oe# setup time to we# active min 4 us t csp ce# setup time to we# active min 4 us t st voltage setup time min 4 us
esi esi 51 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. a <20:12> oe# we# reset# ce# vcc figure 32. sector unprotection timings (a9 high-voltage method) t wpp2 0x00 t st dq sa0 t oe sa1 t oesp t csp t st t vidr t vidr a <0> a <1> a <6> a <9> v id v id note : it is recommended to verify for all sectors. ac characteristics
esi esi 52 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 sec excludes 00h programming prior to erasure (note 4) chip erase time 50 sec byte program time 6 150 us exclude system level overhead (note 5) accelerated byte/word program time 4 120 us word program time 8 210 us chip program time (note 3) byte mode 25 76 sec word mode 17 50 notes: 1. typical program and erase times assume the following conditions: 25 o c, vcc = 3.0v, 10,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90 o c, vcc = 2.7v, 100,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip pr ogramming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algori thm, all bytes are progra mmed to 00h before erasure. 5. system-level overhead is the time required to execute the two-or -four-bus-cycle sequence for the program command. see table 9 for further i nformation on command definitions. 6. the device has a minimum erase and program cycle endur ance of 100,000 cycles . description min max input voltage with respect to vss on all pins exc ept i/o pins (including a9, oe#, and reset#) - 1.0v 12.5v input voltage with respect to vss on all i/o pins - 1.0v vcc + 1.0v vcc current - 100ma +100ma note: includes all pins except vcc. test conditions: vcc = 3.0 v, one pin at a time parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf fbga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf fbga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf fbga 3.9 4.7 pf table 21. latchup characteristics table 22. tsop and bga package capacitance notes: 1. sampled, not 100% tested 2. test conditions ta = 25 o c, f=1.0mhz . parameter description test conditions min unit minimum pattern data retention time 150 o c 10 years 125 o c 20 years table 23. data retention table 20. erase and programming performance
esi esi 53 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. parallel to seating plane ? l r c 0.25mm (0.0098?) bsc b b a see detail a detail a -a- -b- see detail b d1 d n 2 ---- n 2 ---- 1 + a2 0.10 c e a1 -c- seating plane gauge plane -x- e/2 x = a or b b c1 b1 (c) with plating base metal detail b section b-b 0.08mm (0.0031?) m c a-b s 2 1 n e 5 4 5 9 67 7 package ts 48 jedec mo-142 (b) dd symbol min nom max a - - 1.20 a1 0.05 - 0.15 a2 0.95 1.00 1.05 b1 0.17 0.20 0.23 b 0.17 0.22 0.27 c1 0.10 - 0.16 c 0.10 - 0.21 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 e 11.90 12.00 12.10 e 0.50 basic l 0.50 0.60 0.70 r 0.08 - 0.20 n48 0 5 3 notes: 1. controlling dimensions are in millimeters(mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) 2. pin 1 identifier for standard pin out (die up). 3. pin 1 identifier for reverse pin out (die down): ink or laser mark 4. to be determined at the seating plane. the seating plane is def- ined as the plane of contac t that is made when the package lea- ds are allowed to rest freely on a flat horizontal surface. 5. dimension d1 and e do not include mold protrusion. allowable mold protrusion is 0.15mm (0.0059?) per side. 6. dimension b does not include dambar protrusion. allowable dambar protrusion sha ll be 0.08mm (0.0031?) total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07mm (0.0028?). 7. these dimensions apply to the flat section of the lead between 0.10mm (0.0039?) and 0.25mm (0.0098?) from the lead tip. 8. lead coplanarity shall be wi thin 0.10mm (0.004?) as measured from the seating plane. 9. dimension ? e ? is measured at the centerline of the leads. physical dimensions 48-pin standard tsop (m easured in millimeters)
esi esi 54 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. package xfbd 048 jedec n/a 6.00 mm x8.00 mm package symbol min nom max note a 1.10 overall thick ness a1 0.21 0.25 0.29 ball height a2 0.7 0.76 0.82 body thickness d 8.00 bsc body size e 6.00 bsc body size d1 5.60 bsc ball footprint e1 4.00 bsc ball footprint md 8 row matrix sized direction me 6 row matrix sized direction n 48 total ball count b 0.30 0.35 0.40 ball diameter e 0.80 bsc ball pitch sd / se 0.40 bsc solder ball placement notes: 1. dimensioning and toleran cing per asme y14.5m-1994 2. all dimensions are in millimeters. 3. ball position designati on per jesd 95-1, spp-010. 4. e represents the sol der ball grid pitch. 5. symbol ? md ? is the ball row matrix size in the ? d ? direction. symbol ? me ? is the ball column matrix size in the ? e ? direct- ion. n is the maximum number of sol der balls for matrix si- ze md x me . 6. dimension ? b ? is measured at the maximum ball diameter in a plane parallel to datum z . 7. sd and se are measured with respect to datums a and b and define the position of the center solder ball in the out- er row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000 when there is an even number of solder balls in the outer row, sd or se = e /2 8. ? x ? in the package variations denotes part is outer qualifi- cation. 9. ? + ? in the package drawing in dicate the theoretical center of depopulated balls. 10. for package thickness a is the controlling dimension. 11. a1 corner to be indentified by chamfer, ink mark, metalli- zed markings indention or other means. physical dimensions 48-ball fbga (6 x 8 mm) 1 2 3 4 5 6 hfe g dcb a d a e a1 corner index mark 11 b d1 se 7 e1 pin 1 id. sd 7 6 a a1 10 a2 z 0.20 0.08 z 0.25 z (4x) // b 0.15 m z a b 0.08 m z e
esi esi 55 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. ordering information standard products esi standard products are available in several package and operating ranges. the order number (valid combi- nation) is formed by a combination of the following: temperature range blank : commercial (0 o c to + 70 o c) i : industrial (- 40 o c to + 85 o c) package type t : standard tsop (48-pin) w : fbga (48-ball) speed option 70 : 70ns 90 : 90ns sector architecture blank : uniform sector t : top sector b : bottom sector excel semiconductor component group 29 : flash memory technology d : 0.18um e : 0.18um (2nd gen.) f : 0.13um density & organization 400 : 4m ( x8 / x16) 800 : 8m ( x8 / x16) 160 : 16m ( x8 / x16) 320 : 32m ( x8 / x16) 640 : 64m ( x8 / x16) power supply and interface f : 5.0v lv : 3.0v dl : 3.0v, dual bank ds : 1.8v, dual bank bds : 1.8v, burst mode, dual bank es 29 lv 320 x x - xx x x x x pb-free c : pb product g : pb-free product voltage range blank : 2.7v ~ 3.6v
esi esi 56 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. part no. es29lv320et-70tgi es29lv320et-70tci es29lv320eb-70tgi es29lv320eb-70tci es29lv320et-90tgi es29lv320et-90tci es29lv320eb-90tgi es29lv320eb-90tci es29lv320et-70wgi es29lv320et-70wci es29lv320eb-70wgi es29lv320eb-70wci es29lv320et-90wgi es29lv320et-90wci es29lv320eb-90wgi es29lv320eb-90wci speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns vcc 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v boot sector to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom package 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga pb pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - ball pitch/size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm body size 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm product selection guide industrial device
esi esi 57 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. part no. es29lv320et-70tg es29lv320et-70tc es29lv320eb-70tg es29lv320eb-70tc es29lv320et-90tg es29lv320et-90tc es29lv320eb-90tg es29lv320eb-90tc es29lv320et-70wg es29lv320et-70wc es29lv320eb-70wg es29lv320eb-70wc es29lv320et-90wg es29lv320et-90wc es29lv320eb-90wg es29lv320eb-90wc speed 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns 70ns 70ns 70ns 70ns 90ns 90ns 90ns 90ns vcc 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v 2.7 - 3.6v boot sector to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom to p to p bottom bottom package 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-pin tsop 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga 48-ball fbga pb pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - pb-free - ball pitch/size 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm 0.8mm/0.3mm body size 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm 6mm x 8mm product selection guide commercial device
esi esi 58 rev. 0a may 25, 2006 es29lv320e excel semiconductor inc. document title 32m flash memory revision history revision number data items rev. 0a may. 25, 2006 initial release version. excel semiconductor inc. 1010 keumkang hightech valley, sangdaewon1-dong 13 3-1, jungwon-gu, seongnam-si, kyongki-do, rep. of korea. zip code : 462-807 tel : +82-31-777-5060 fax : +82-31-740-3798 / homepage : www.excelsemi.com the attached datasheets are provided by excel semiconductor.inc (esi). esi reserves the right to change the spec- ifications and products. esi will answer to your qu estions about device. if you have any questions, please contact the esi office.

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